1. Field of the Invention
This invention relates to digital-to-analog converters (DACs), and more particularly to mismatch-shaping DACs.
2. Description of Related Art
Data converters, both digital-to-analog converters (DACs) and analog-to-digital converters (ADCs), are ubiquitous in applications involving digital signal processing of real-world signals such as those found in communication systems, instrumentation, and audio and video processing systems. A class of data converters referred to as delta-sigma data converters are widely used in many such applications requiring mododerate to high precision, and having low to moderate signal bandwidths. Using well known techniques such as oversampling relative to the bandwidth of the signal to be converted, coarse internal quantization, and quantization noise-shaping, delta-sigma data converters perform high-precision data conversion functions in VLSI circuits that are optimized for digital circuitry. While coarse quantization is used to simplify analog processing within the data converter, oversampling and quantization noise-shaping techniques are used to achieve high precision data conversion despite errors introduced by the coarse quantization.
As is well known in the VLSI circuit design arts, owing to a high sensitivity to analog component mismatches and other circuit errors present in at least one of the internal DACs, non-linearity is introduced into the signal of interest. Unlike other noise sources, the non-linearity, which can be modeled as additive error and is referred to as xe2x80x9cDAC noisexe2x80x9d, is not attenuated by the processing chain and therefore directly degrades the overall signal-to-noise ratio (SNR) of the data converter. For example, and as described in more detail below with reference to the ADC 700 (of FIG. 7), the output of a feedback DAC 712 is subtracted directly from the input signal (provided on input line 716) via an adder 702. Any error that is introduced by the feedback DAC 712 is directly added to the input signal. Any distortion introduced by the DAC 712 is regarded as an integral part of the input signal itself, as it possesses the same transfer function to the output. Therefore, the portion of this error within the passband of the decimation filter 714 directly degrades the overall conversion accuracy.
To overcome the non-linearity introduced by the mismatched components, until recently the majority of delta-sigma data converters were designed using internal one-bit DACs. While one-bit DACs effectively overcame the component mismatching problem, they force design tradeoffs to be made that, for a given oversampling level, significantly reduce the data conversion SNR below what is achievable using multi-bit quantization. With this in mind, various xe2x80x9cmismatch-shapingxe2x80x9d DAC architectures have been developed. These architectures use digital algorithms to perform spectral shaping of noise introduced by non-ideal analog circuit behavior. The algorithms require no specific knowledge of the particular analog errors introduced by the circuit. In these applications, digital signal processing (DSP) techniques are used to shape the errors such that most of their energy lies outside of the data converter signal band. Component mismatches are accepted as inevitable, but their negative effects are mitigated by the DSP techniques.
One prior art mismatch-shaping DAC architecture is described in a paper written by Dr. Ian Galton, entitled xe2x80x9cSpectral Shaping of Circuit Errors in Digital-to-Analog Convertersxe2x80x9d, published in the IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, Vol. 44, No.: 10, October 1997, referred to below as the Galton paper, and incorporated by reference in its entirety for its teachings on mismatch-shaping DACs. The DAC architectures described in this paper are also set forth in Dr. Galton""s patent, U.S. Pat. No. 5,684,482, issued Nov. 4, 1997, also incorporated in its entirety herein for its teachings on mismatch-shaping DAC architectures. A DAC topology is described in both of the incorporated references that spectrally shapes the DAC noise caused by analog circuit component mismatches. As described in the incorporated U.S. patent, most of the mismatch-shaping DAC architectures generally take the form of the prior art DAC architecture 100 of FIG. 1.
As shown in the FIG. 1, the prior-art mismatch-shaping DAC architecture 100 typically includes a digital encoder 5 and N one-bit DACs referred to as unit DAC-elements 6. A digital input sequence x[n] is taken to be a sequence of non-negative integers less than or equal to N. Those of ordinary skill in the DAC design arts shall recognize that the digital input sequence can also comprise a signed representation. The sequence is provided as input to an input 9 of the digital encoder 5. The digital encoder 5 maps each input sample to N outputs x1[n], x2[n], . . . xN[n] 10 such that the sum of the N outputs is equal to x[n]:
x1[n]+x2[n]+x3[n]+. . . +xN[n]=x[n]xe2x80x83xe2x80x83Equation 1
Each output bit xi[n] is provided as a corresponding input 12 to the unit DAC-elements 6. The unit DAC-elements 6 operate to create N output signals y1[n], y2[n], yN[n] on respective outputs 16. Each output signal yr[n] is then provided as an input to an adder 19 which sums the outputs to create an analog signal y[n] on an output 20.
The digital encoder 5 sets x[n] of its N output bits to be high, and the remaining Nxe2x88x92x[n] of its N output bits are set low. This enables 1-bit DACs 6 appropriately to convert the digital signal to a numerically equivalent analog output signal. If the 1-bit DACs 6 were to introduce no errors into their respective output signals, the output 20 y[n] of the DAC 100 would equal the input 9, x[n], exactly. However, in practice, the errors are not zero because of the non-ideal circuit behavior described above. Non-ideal circuit behavior results in a gain error, a non-zero DC offset, and non-zero DAC noise.
The digital encoder 5 can be implemented in a variety of ways to select its output bits xi[n] and satisfy Equation 1 (above). Thus, the digital encoder 5 can modulate the DAC noise component of y[n] without affecting the signal component. The mismatch-shaping DACs perform this modulation such that the DAC noise is spectrally shaped in a manner that is similar to delta-sigma modulator quantization noise.
Another exemplary mismatch-shaping DAC topology 100xe2x80x2 is described in the incorporated U.S. patent and shown in FIG. 2. The number format used to represent the digital input value is unimportant as any convenient digital representation can be used. In the example shown in FIG. 2, the input bus 113 is 4-bits wide to accommodate the possibility of the number eight, represented by the binary number 10002. The topology 100xe2x80x2 is a special case of the topology 100 shown in FIG. 1. As shown in FIG. 2 and described in more detail in the incorporated patent, the digital encoder 5 of FIG. 1 is replaced with the digital logic 110 of FIG. 2. The digital logic 110 of FIG. 2 comprises three layers of digital devices called switching blocks 120-126 and labeled Skr, where k denotes a layer number and r denotes a position of the switching block 120-126 in its respective layer. Additionally, the topology 100xe2x80x2 includes eight one-bit DACs 130-137 coupled to an adder 169. A digital signal x[n] is input into the switching block 120 via an input bus 113. The switching block 120 splits the input signal into two 3-bit output signals on outputs 140 and 141. The signal on output 140 is fed to an input 142 of the switching block 121, while the signal on output 141 is fed to an input 143 of the switching block 122. The switching blocks 121 and 122 receive the respective three-bit signals on the inputs 142 and 143 and split them into four two-bit output signals on outputs 144-147. These output signals are applied as inputs 148-151 of the next layer of switching blocks comprising the blocks 123-126. In particular, the signal on the output 144 from the switching block 121 is fed to the input 148 of the switching block 123; the signal on the output 145 from the switching block 121 is fed to the input 149 of the switching block 124; the signal on the output 146 from the switching block 122 is fed to the input 150 of the switching block 125; and the signal on the output 147 from the switching block 122 is fed to the input 151 of the switching block 126. The switching blocks 123-126 convert the four two-bit signals on the inputs 148-151 into eight one-bit signals on the outputs 152-159. These one-bit signals are represented as x1[n], x2[n], . . . x8[n], respectively. As described in detail in the incorporated U.S. patent, the switching blocks 120-126 must satisfy a number conservation rule which states that two outputs of each switching block must be in the range of {0, 1, . . . , 2kxe2x88x921} where k is the layer number (i.e., Layer 1, Layer 2, Layer 3, etc.), and the sum of the outputs must equal the value of the input to the switching block.
The complexity of the prior art digital encoders increases exponentially with the number of input bits. Consequently, as the number of input bits increases, the prior art mismatch-shaping DACs require that an increased portion of integrated circuit area be dedicated for the digital encoder logic function. In addition, the digital logic used to implement the encoder introduces undesirable signal propagation delays and increased power dissipation into the overall DAC architecture. Propagation delays are particularly problematic in high speed delta-sigma ADC designs as signals are often required to propagate through the digital encoder in significantly less than one clock cycle. Therefore, any propagation delay introduced by the digital encoder can limit the performance capabilities of the DAC.
The inventors have observed that, for some applications, and particularly for applications wherein peak signal-to-noise ratio (SNR) is a less important DAC performance criterion than dynamic range (where dynamic range is defined as the range over which the signal can be processed with xe2x80x9cacceptablexe2x80x9d SNR, as determined from system requirements), the mismatch-shaping function should be fully effective when the input signal amplitude level is relatively low (i.e., close to xe2x80x9cmid-scalexe2x80x9d). However, for these applications, the mismatch-shaping function can be less effective when the input signal amplitude level is relatively high. For example, in some wireless communication applications such as those designed in compliance with the well-known xe2x80x9cBluetoothxe2x80x9d wireless LAN standard, mismatch-shaping of DAC noise is important when the input signal amplitude level is low. In wireless devices designed for the Bluetooth specification, for example, errors introduced by DAC component mismatches can be tolerated when the input amplitude level is relatively large, however the errors can be problematic when the input amplitude level is relatively low. The SNR curves of three exemplary mismatch-shaping DACs are shown in FIG. 3.
FIG. 3 shows a plot 30 of an input signal power level versus signal-to-noise ratio (SNR) (which is proportional to the square of the amplitude) for various mismatch-shaping DACs. As shown in FIG. 3, an ideal plot of the input signal versus SNR is a straight line 32 having a slope of one. More realistic curves 34 and 36 show how the SNR of the DACs can be affected by conversion noise. Curve 34 shows a plot of the input signal versus SNR for a prior art mismatch-shaping DAC wherein mismatch shaping is implemented over the full input signal range. Curve 36 shows a plot of the input signal versus SNR for a xe2x80x9cpartiallyxe2x80x9d mismatch-shaping DAC wherein mismatch shaping is fully implemented only for input signals within a restricted range about the mid-scale point. As shown in FIG. 3, for larger amplitude levels, the peak SNR is reduced in curve 36 as compared with peak SNRs for equivalent amplitude levels in the curves 32 and 34. However, as described above, in some applications, the dynamic range shown in curve 36 is sufficient to meet the data conversion requirements. By fully implementing mismatch shaping only for those input signals that fall within a restricted range about the mid-scale point (i.e., by xe2x80x9cpartially mismatch-shapingxe2x80x9d the input signals) as shown in curve 36, and thereby only partially mismatch-shaping the DAC conversion noise, a design tradeoff is possible which reduces the complexity of the digital encoder at the sacrifice of reduced SNR for larger-amplitude input signals. In some applications, this design tradeoff is an attractive alternative to the use of prior art mismatch-shaping DACs.
The present invention provides an inventive partial mismatch-shaping DAC architecture that spectrally shapes the DAC noise contributed by component mismatches.
A novel partial mismatch-shaping DAC architecture is described. The partial mismatch-shaping DAC spectrally shapes data converter errors caused by mismatched components. In some applications, a design tradeoff can be made whereby only a subset of internal DACs are mismatch-shaped. In these applications, the mismatch-shaping function is fully effective when the input amplitude level is relatively low, however, the mismatch-shaping function is not fully effective when the input amplitude level is high. This results in savings in complexity, reduced power dissipation and shortened propagation delays associated with the DAC digital logic circuitry.
The inventive DAC includes a digital encoder including at least one pass-through encoding block and a mismatch-shaping logic block. The DAC also includes a plurality of internal one-bit DAC elements, the outputs of which are coupled to an adder. The input to the inventive DAC is divided into input signal components. In one embodiment, the input is split into three components: xHIGH[n], xMID[n], and xLOW[n]. The high and low components, xHIGH[n], and xLOW[n], respectively, comprise amplitude levels of the input signal that are relatively large in magnitude (relative to mid-scale). The middle component xMID[n] comprises amplitude levels of the input signal that are relatively small in magnitude (i.e., input signal amplitude levels close to mid-scale). In accordance with the present inventive DAC, mismatch-shaping is performed only on the middle component xMID[n]. Mismatch-shaping is not performed on the high and low components xHIGH[n], and xLOW[n], or on their associated internal DAC inputs.
The inventive DAC can be used in implementing internal DACs of delta-sigma ADCs and delta-sigma DACs. Exemplary delta-sigma ADC and DAC architectures adapted, for use with the present inventive DAC are also described.